1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor memory device having a split hierarchical power supply structure.
2. Description of the Prior Art
(1) Prior Art 1
In a recent CMOS semiconductor integrated circuit device, a device such as a MOS transistor is now being refined while the power supply voltage therefor is reduced in order to improve the reliability of the refined device and reduce power consumption. The threshold voltage Vth of the MOS transistor is also reduced for performing a high-speed operation with the low power supply voltage.
If the threshold voltage Vth of the MOS transistor is reduced, however, a subthreshold leakage current flowing between its source and drain is increased when the MOS transistor is non-conductive. This leads to increase of the direct current consumed by the overall CMOS semiconductor integrated circuit device, particularly in a standby state. In order to solve this problem, an MT-CMOS (multi-threshold CMOS) system has been proposed.
FIG. 60 is a circuit diagram showing a principal part of a CMOS semiconductor integrated circuit device employing the MT-CMOS system. Referring to FIG. 60, the CMOS semiconductor integrated circuit device includes a CMOS logic circuit (invertor INV in FIG. 60) formed by a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1 having low threshold voltages LVthp and LVthn respectively and a P-channel MOS transistor QP2 having a relatively high threshold voltage MVthp.
The P-channel MOS transistor QP1 and the N-channel MOS transistor QN1 are serially connected between a power supply node N1 and a ground node N2 of the invertor INV while the gates thereof are connected to an input node N3 of the invertor INV and the drains thereof form an output node N4 of the invertor INV. The P-channel MOS transistor QP2 is connected between a line of a power supply potential Vcc and the power supply node N1 of the invertor INV, and its receives a chip selection signal /CS. The ground node N2 of the invertor INV is connected to a line of a ground potential GND.
In an active state, the signal /CS goes low for activation and the P-channel MOS transistor QP2 is rendered conductive for supplying the power supply potential Vcc to the power supply node N1 of the invertor INV. When an input signal VI for the invertor INV falls from a high level to a low level, the P-channel MOS transistor QP1 is rendered conductive and the N-channel MOS transistor QN1 is rendered non-conductive so that an output signal VO from the invertor INV goes high. At this time, a high-speed operation is attained due to the low threshold voltages LVthp and LVthn of the P-channel MOS transistor QP1 and the N-channel MOS transistor QN1.
In a standby state, the signal /CS goes high for inactivation and the P-channel MOS transistor QP2 is rendered non-conductive for stopping the supply of the power supply potential Vcc to the power supply node N1 of the invertor INV. The input signal VI rises from the low level to a high level, the P-channel MOS transistor QP1 is rendered non-conductive and the N-channel MOS transistor QN1 is rendered conductive so that the output signal VO goes high. While a subthreshold leakage current flows from the line of the power supply potential Vcc to the line of the ground potential GND through the MOS transistors QP2, QP1 and QN1 at this time, this subthreshold leakage current is suppressed low due to the presence of the P-channel MOS transistor QP2 having the relatively high threshold voltage MVthp.
(2) Prior Art 2
When the threshold value of a transistor is reduced following refinement of the transistor and reduction of a power supply voltage, the value of a subthreshold current flowing in an OFF state of the transistor is increased. Japanese Patent Laying-Open No. 6-237164 (1994) discloses an SCRC (subthreshold current reduction control) technique for reducing such a subthreshold current. According to this SCRC technique, switches are inserted between a CMOS invertor circuit and a power source and between the CMOS invertor circuit and the ground respectively. In an active state, both switches are turned on so that the invertor circuit supplies an output signal in response to an input signal as general. When the invertor circuit supplies an output signal of a high logical level in a standby state, the switch for the power source is turned on while that for the ground is turned off.
A subthreshold current flowing through an N-channel MOS transistor provided in the invertor circuit is reduced since the switch for the ground is turned off. When the invertor circuit supplies an output signal of a low logical level in the standby state, on the other hand, the switch for the power source is turned off and that for the ground is turned on. In this case, a subthreshold current flowing through a P-channel MOS transistor provided in the invertor circuit is reduced since the switch for the power source is turned off.
Japanese Patent Laying-Open No. 6-203558 (1994) discloses a dynamic random access memory (DRAM) employing the aforementioned SCRC technique. In this DRAM, a word line driver is split into blocks, so that each block is provided with a plurality of word line drivers and a sub power supply line connected to these word line drivers in common. Each sub power supply line is connected to a main power supply line in common through a selection transistor. Each selection transistor is turned on when the corresponding block is in an active state, and turned off when in a standby state. In a block of a standby state, therefore, subthreshold currents flowing through the word line drivers are reduced.
(3) Prior Art 3
FIG. 61 is a circuit diagram showing a principal part of a CMOS semiconductor integrated circuit device employing the so-called hierarchical power supply system. Referring to FIG. 61, the CMOS semiconductor integrated circuit device includes main power supply lines ML, main ground lines MLxe2x80x2, a sub power supply line SL, a sub ground line SLxe2x80x2, a P-channel MOS transistor QP5, an N-channel MOS transistor QN5 and a plurality of invertors INV1, INV2, . . . The P-channel MOS transistor QP5 and the N-channel MOS transistor QN5 have relatively high threshold voltages MVthp and MVthn respectively. The invertors INV1, INV2, . . . are formed by P-channel MOS transistors and N-channel MOS transistors having relatively low threshold voltages LVthp and LVthn respectively, similarly to the invertor INV shown in FIG. 60.
Each main power supply line ML is externally supplied with a power supply potential Vcc. The P-channel MOS transistor QP5 is connected between the main power supply line ML and the sub power supply line SL, and its gate receives an inverted signal /xcfx86a of an activation signal xcfx86a.
Each main ground line MLxe2x80x2 is externally supplied with a ground potential GND. The N-channel MOS transistor Qn5 is connected between the main ground line MLxe2x80x2 and the sub ground line SLxe2x80x2, and its gate receives the activation signal xcfx86a.
As shown in FIGS. 62A and 62B, the activation signal xcfx86a goes low in a standby state and high in an active state. The MOS transistors QP5 and QN5 are turned off in the standby state to disconnect the sub power supply line SL and the sub ground line SLxe2x80x2 from the main power supply line ML and the main ground line MLxe2x80x2 respectively, while the MOS transistors QP5 and QN5 are turned on in the active state to connect the sub power supply line SL and the sub ground line SLxe2x80x2 to the main power supply line ML and the main ground line MLxe2x80x2 respectively.
The invertors INV1, INV2, . . . are serially connected with each other. A signal VI is inputted in the initial-stage invertor INV1. The signal VI goes low in the standby state and high in the active state.
Power supply nodes of the odd-stage invertors INV1, INV3, . . . whose P-channel MOS transistors are rendered conductive in the standby state to output high levels are connected to the main power supply lines ML, and ground nodes thereof are connected to the sub ground line SLxe2x80x2.
Power supply nodes of the even-stage invertors INV2, INV4, . . . whose N-channel MOS transistors are rendered conductive in the standby state to output low levels are connected to the sub power supply line SL and ground nodes thereof are connected to the main ground lines MLxe2x80x2.
In the standby state, the main power supply lines ML and the main ground lines MLxe2x80x2 are disconnected from the sub power supply line SL and the sub ground line SLxe2x80x2 respectively, to reduce standby currents, i.e., subthreshold leakage currents of the MOS transistors included in the invertors INV1, INV2, . . . At this time, the outputs of the invertors INV1, INV2, . . . are not unstabilized since the power supply nodes of the invertors INV1, INV3, . . . outputting high levels are connected to the main power supply lines ML while the ground nodes of the invertors INV2, INV4, . . . outputting low levels are connected to the main ground lines SL.
In the active state, the main power supply lines ML and the main ground lines MLxe2x80x2 are connected with the sub power supply line SL and the sub ground line SLxe2x80x2 respectively, to supply the invertors INV1, INV2, . . . with the power supply potential Vcc and the ground potential GND. The invertors INV1, INV2, . . . , which are formed by the P-channel MOS transistors and the N-channel MOS transistors having the relatively low threshold voltages LVthp and LVthn respectively, operate at a high speed.
However, the CMOS semiconductor integrated circuit device shown in FIG. 60 regularly renders the P-channel MOS transistor QP2 conductive in the active state even if the invertor INV may not be supplied with the power supply potential Vcc (the signal VI is at a high level), and still consumes a large current.
Although the SCRC technique can reduce a subthreshold current flowing in a standby state as described above, the voltage of a sub power supply line, electrically disconnected from a main power supply line in the standby state, remarkably lowers from a power supply voltage in the standby state. while the sub power supply line is connected to the main power supply line when the standby state is converted to an active state, a prescribed time is required for the voltage of the sub power supply line to reach the power supply voltage. Immediately after entering the active state, therefore, a logic circuit connected to the sub power supply line cannot correctly operate.
Japanese Patent Laying-Open No. 8-83487 (1996) discloses a method for solving this problem. According to this method, a voltage set circuit is provided for setting the voltage of a main power supply line at a prescribed level lower than a power supply voltage. However, this voltage set circuit operates not only in a standby state but also in an active state, and hence consumes large current.
In the CMOS semiconductor integrated circuit shown in FIG. 61, the sub power supply line SL and the sub ground line SLxe2x80x2 require a certain degree of time for reaching the power supply potential Vcc and the ground potential GND after the MOS transistors QP5 and QN5 are turned on in a first active cycle after power supply, and hence the circuit operation is disadvantageously retarded to cause a malfunction.
Accordingly, an object of the present invention is to provide a semiconductor memory device and a semiconductor device having small current consumption.
Another object of the present invention is to provide a semiconductor integrated circuit device preventing delay in operation of a logic circuit following a split hierarchical power supply structure.
Still another object of the present invention is to provide a semiconductor integrated circuit device having a split hierarchical power supply structure preventing increase of power consumption.
According to an aspect of the present invention, a first transistor rendered conductive in response to an address signal is connected between a main power supply line and a sub power supply line, and a decoder is driven by a power supply potential supplied from the main power supply line through the sub power supply line to set a memory cell selection line at a selection potential in response to the address signal. Thus, the decoder is supplied with the power supply potential only when the address signal is inputted, whereby a subthreshold leakage current flowing in the decoder is reduced as compared with the prior art supplying a power supply potential to a decoder in an active period even if no address signal is inputted, and current consumption is reduced.
Preferably, a plurality of memory cells are split into a plurality of groups, a specific group selection signal included in the address signal is allocated to each group, the first transistor and the sub power supply line are provided in correspondence to each group, and the first transistor is rendered conductive in response to the corresponding group selection signal. Thus, the decoder is supplied with the power supply potential only when the corresponding group selection signal is inputted while that of a non-selected group is supplied with no power supply potential, whereby the current consumption is further reduced.
Preferably, a plurality of memory cells are split into a plurality of groups, a specific group selection signal included in the address signal is allocated to each group, and a second transistor is further provided in correspondence to each group. The second transistor is connected between a part of the sub power supply line close to the corresponding decoder and the main power supply line, and rendered conductive in response to the corresponding group selection signal. In this case, the potential of an end portion of the sub power supply line is prevented from reduction by the impedance of the sub power supply line.
Preferably, the decoder includes a logic circuit outputting a memory cell selection signal in response to the corresponding address signal and a third transistor connected between the sub power supply line and the corresponding memory cell selection line and rendered conductive in response to the memory cell selection signal. In this case, the decoder can be readily structured.
Preferably, the threshold voltage of the third transistor is rendered smaller than that of the first transistor. In this case, the first transistor can reduce the subthreshold leakage current and the operating speed of the third transistor can be increased.
Preferably, the threshold voltage of the third transistor is equal to that of the first transistor. In this case, the first and third transistors can be readily formed.
Preferably, a plurality of third transistors are arranged at the same pitch as a plurality of memory selection lines, and the first transistor is dispersively arranged between the plurality of third transistors. If the first transistor is concentrically arranged, a circuit connected to the sub power supply line on a position separated from the concentrically arranged first transistor is inferior in current drivability to a circuit connected to the sub power supply line on a position close to the concentrically arranged first transistor, due to influence by the resistance of the sub power supply line. According to the present invention, however, a plurality of circuits connected to the sub power supply line have high current drivability equivalent to that of the circuit connected to the sub power supply line on the position close to the concentrically arranged first transistor, due to the dispersive arrangement of the first transistor. Further, area penalty may be small due to the dispersive arrangement.
Preferably, the first transistor is rendered conductive only for a prescribed time in response to supply of the power supply potential to the main power supply line. Thus, the sub power supply line is precharged in power supply, whereby the decoder is not delayed in operation to cause a malfunction even if the address signal is first inputted upon power supply.
According to another aspect of the present invention, a plurality of memory arrays each split into a plurality of memory blocks are provided while a first sub power supply line and a first transistor is provided in correspondence to each memory block. The first transistor is connected between a main power supply line and the corresponding first sub power supply line and rendered conductive in response to corresponding memory array selection signal and block selection signal, while a first decoder receives a power supply potential from the corresponding first sub power supply line and sets a corresponding memory cell selection line at a selection potential in response to corresponding memory array selection signal and address signal. Thus, the first decoder is supplied with the power supply potential only when the corresponding block selection signal is inputted while no power supply potential is supplied to those of non-selected memory arrays, whereby subthreshold leakage currents in the first decoders are reduced as compared with the prior art supplying all first decoders with a power supply potential in an active period, and current consumption is reduced.
Preferably, the first decoder includes a logic circuit responsively outputting a memory cell selection signal when the corresponding memory array selection signal and address signal are inputted and a second transistor connected between the corresponding first sub power supply line and the corresponding memory cell selection line and rendered conductive in response to the memory cell selection signal. In this case, the first decoder can be readily structured.
Preferably, the threshold voltage of the second transistor is rendered smaller than that of the first transistor. In this case, the first transistor can reduce the subthreshold leakage current and the operating speed of the second transistor can be increased.
Preferably, the threshold voltage of the second transistor is equal to that of the first transistor. In this case, the first and second transistors can be readily formed.
Preferably, the second transistors are arranged at the same pitch as a plurality of memory cell selection lines, and the first transistor is dispersively arranged between the plurality of second transistors. If the first transistor is concentrically arranged, a circuit connected to a sub power supply line on a position separated from the concentrically arranged first transistor is inferior in current drivability to a circuit connected to the sub power supply line on a position close to the concentrically arranged first transistor. According to the present invention, however, a plurality of circuits connected to the first sub power supply line have high current drivability equivalent to that of the circuit connected to the sub power supply line on the position close to the concentrically arranged first transistor, due to the dispersive arrangement of the first transistor. Further, area penalty may be small due to the dispersive arrangement.
Preferably, a third transistor and a second sub power supply line are further provided in correspondence to at least two memory blocks. The third transistor is connected between the main power supply line and the second sub power supply line and responsively rendered conductive when at least one of the corresponding memory array selection signal and block selection signal is inputted. The logic circuit of the first decoder receives the power supply potential from the corresponding second sub power supply line. In this case, a subthreshold leakage current in the logic circuit can be suppressed small for further reducing power consumption.
Preferably, a second decoder is further provided in correspondence to each memory array for generating the block selection signal in accordance with the corresponding memory array selection signal and address signal and supplying the same to an input electrode of the corresponding first transistor. In this case, the block selection signal can be quickly generated for quickly rendering the first transistor conductive.
Preferably, the first transistor is responsively rendered conductive by a prescribed time when the main power supply line is supplied with the power supply potential. Thus, the sub power supply line is precharged in power supply, whereby the first decoder is not delayed in operation to cause a malfunction even if the address signal is first inputted upon power supply.
According to still another aspect of the present invention, first and second transistors rendered conductive in response to an active signal are connected between a main power supply line and first and second sub power supply lines respectively. A decoder and a redundancy decoder are driven by a power supply potential supplied from the main power supply line through the first and second sub power supply lines respectively. Thus, the decoder and the redundancy decoder are supplied with the power supply potential only when the address signal is inputted, whereby subthreshold leakage currents in the decoder and the redundancy decoder are reduced as compared with the prior art supplying a power supply potential to a decoder and a redundancy decoder in an active period even if no address signal is inputted, and current consumption is reduced.
Preferably, the decoder is responsively inactivated when a corresponding determination circuit outputs a hit signal. Data is read/written from/in either a memory cell or a spare memory cell, and hence no data collision can take place.
Preferably, the decoder includes a logic circuit responsively outputting a memory cell selection signal when the corresponding address signal is inputted and a third transistor connected between the first sub power supply line and a corresponding memory cell selection line and rendered conductive in response to the memory cell selection signal, and the redundancy decoder includes a fourth transistor connected between the second sub power supply line and a spare memory cell selection line and rendered conductive in response to the hit signal. In this case, the decoder and the redundancy decoder can be readily structured.
Preferably, the threshold voltages of the third and fourth transistors are smaller than those of the first and second transistors respectively. In this case, the first and second transistors can reduce subthreshold leakage currents and the operating speeds of the third and fourth transistors can be increased.
Preferably, the threshold voltages of the third and fourth transistors are equal to those of the first and second transistors respectively. In this case, the first to fourth transistors can be readily structured.
Preferably, the first and second transistors are responsively rendered conductive for a prescribed time when the main power supply line is supplied with a power supply potential. Thus, the sub power supply line is precharged in power supply, whereby the decoder and the redundancy decoder are not delayed in operation to cause a malfunction even if the address signal is first inputted upon power supply.
According to a further aspect of the present invention, a transistor rendered conductive in response to an address signal is connected between a main power supply line and a sub power supply line, while a decoder and a redundancy decoder are driven by a power supply potential supplied from the main power supply line through the sub power supply line for setting a memory cell selection line and a spare memory cell selection line at a selection potential in response to the address signal. Thus, the decoder and the redundancy decoder are supplied with the power supply potential only when the address signal is inputted, whereby subthreshold leakage currents in the decoder and the redundancy decoder are reduced as compared with the prior art supplying the power supply potential to the decoder and the redundancy decoder in an active period even if no address signal is inputted, and current consumption is reduced.
Preferably, the transistor is responsively rendered conductive only for a prescribed time when the main power supply line is supplied with the power supply potential. Thus, the sub power supply line is precharged in power supply, whereby the decoder and the redundancy decoder are not delayed in operation to cause a malfunction even if the address signal is first inputted upon power supply.
In a semiconductor device having a hierarchical power supply structure with a main power supply line and a sub power supply line according to a further aspect of the present invention, a capacitor is connected to the sub power supply line for adding a capacitance other than a parasitic capacitance to the sub power supply line, whereby stability of the sub power supply line can be further improved in driving.
In a semiconductor device having a hierarchical power supply structure with a main power supply line and a sub power supply line according to a further aspect of the present invention, a transistor having high current drivability supplies a current to a part having a large capacitance even if the sub power supply line is split into a plurality of sub power supply lines having different capacitances, whereby the recovery time for a sub power supply line having a large capacitance can be rendered at least equivalent to that for a sub power supply line having a small capacitance.
In a semiconductor device having a hierarchical power supply structure with a main power supply line and a sub power supply line according to a further aspect of the present invention, a transistor having high current drivability supplies a current to a part having a small capacitance even if the sub power supply line is split into a plurality of sub power supply lines having different capacitances, whereby the current drivability of a circuit connected to a sub power supply line having a small capacitance can be rendered at least equivalent to that of a circuit connected to a sub power supply line having a large capacitance.
In a semiconductor device having a hierarchical power supply structure with a main power supply line and a sub power supply line according to a further aspect of the present invention, a first capacitor is connected to a sub power supply line having a small capacitance even if the sub power supply line is split into a plurality of sub power supply lines having different capacitances, whereby the current drivability of a circuit connected to the sub power supply line having a small capacitance can be rendered at least equivalent to that of a circuit connected to a sub power supply line having a large capacitance.
Preferably, a second capacitor is connected to the sub power supply line having a large capacitance. In this case, stability of the sub power supply line having a large capacitance can be improved in driving.
In a semiconductor device having a hierarchical power supply structure with a main power supply line and a sub power supply line according to a further aspect of the present invention, a transistor connected between the main power supply line and the sub power supply line is responsively rendered conductive for a prescribed time when the main power supply line is supplied with a power supply potential, and responsively rendered conductive when a control signal is inputted. Thus, the sub power supply line is precharged in power supply, whereby an internal circuit is not delayed in operation even if the control signal is first inputted upon power supply.
In a semiconductor device having a hierarchical power supply structure with a main power supply line and a sub power supply line according to a further aspect of the present invention, a first transistor connected between the main power supply line and the sub power supply line is responsively rendered conductive for a prescribed time when the main power supply line is supplied with a power supply potential, and rendered conductive in an active mode. Thus, the sub power supply line is precharged in power supply, whereby an internal circuit is not delayed in operation even if the semiconductor device first enters the active mode upon power supply.
Preferably, the internal circuit is an invertor inverting and outputting an input signal and this invertor includes second and third transistors serially connected between the sub power supply line and a second power supply line, while the input signal is held at a first power supply potential in a standby mode and a precharge period. In this case, the output of the invertor is held at a second power supply potential to be not unstabilized.
Preferably, the internal circuit is an invertor inverting and outputting an input signal, the invertor includes second and third transistors serially connected between the sub power supply line and a second power supply line, the absolute value of the threshold voltage of the third transistor is larger than that of the second transistor, and the input signal is held at a first power supply potential in a standby mode and at a second power supply potential in power supply. If transition from an active mode to the standby mode may not be performed at a high speed, current consumption is further reduced due to this structure.
A semiconductor integrated circuit device according to a further aspect of the present invention includes a plurality of internal circuit groups, a main power supply line, and a plurality of sub power supply lines. Each of the internal circuit groups enters an active state or a standby state. The main power supply line receives a power supply voltage. The plurality of sub power supply lines are provided in correspondence to the plurality of internal circuit groups. Each of the internal circuit groups includes a first logic circuit. The first logic circuit is connected to the corresponding sub power supply line for supplying an output signal of the power supply voltage or a ground voltage in response to an input signal in the active state while supplying an output signal of the ground voltage in the standby state. The semiconductor integrated circuit device further includes a plurality of first switching elements and a plurality of first precharge circuits. The plurality of first switching elements are provided in correspondence to the plurality of internal circuit groups. Each of the first switching elements is connected between the main power supply line and the corresponding sub power supply line to be turned on when the corresponding internal circuit group enters the active state and turned off when the same enters the standby state. The plurality of first precharge circuits are provided in correspondence to the plurality of internal circuit groups. Each of the first precharge circuits starts precharging the corresponding sub power supply line toward a first prescribed voltage lower than the power supply voltage and higher than the ground voltage before the corresponding internal circuit group enters the active state.
The aforementioned semiconductor integrated circuit device, starting to precharge the corresponding sub power supply line before each internal circuit group enters the active state, can immediately start operation when the internal circuit group enters the active state.
Preferably, each of the first precharge circuits includes a diode element and a second switching element. The diode element is forwardly connected between the main power supply line and the corresponding sub power supply line. The second switching element is serially connected with the diode element and turned on before the corresponding internal circuit group enters the active state. More preferably, the diode element is a diode-connected transistor.
Thus, a voltage lower than the power supply voltage by the threshold voltage of the diode element is supplied to the sub power supply line for precharging the sub power supply line.
Preferably, each of the first precharge circuits starts the precharging before the corresponding internal circuit group enters the active state, and ends the precharging before the corresponding internal circuit group enters the active state.
Thus, the power necessary for the precharging is suppressed.
Preferably, each of the first precharge circuits starts the precharging before the corresponding internal circuit group enters the active state, and continues the precharging while the corresponding internal circuit group is in the active state.
When the internal circuit group is in the active state, therefore, the precharge circuit can compensate for the corresponding first switching element for the internal circuit group with power.
Preferably, the aforementioned semiconductor integrated circuit device further includes a memory cell array. The memory cell array has a plurality of memory cells arranged in a plurality of rows and a plurality of columns. One of the internal circuit groups includes a row decoder for selecting a row of the memory cell array. Another one of the internal circuit groups includes a column decoder for selecting a column of the memory cell array after operation of the row decoder. The first precharge circuit corresponding to the internal circuit group including the column decoder starts the precharging during operation of the row decoder.
Preferably, the aforementioned semiconductor integrated circuit device further includes a main ground line and a plurality of sub ground lines. The main ground line receives a ground voltage. The plurality of sub ground lines are provided in correspondence to the plurality of internal circuit groups. Each of the internal circuit groups further includes a second logic circuit. The second logic circuit is connected to the corresponding sub ground line for supplying an output signal of the power supply voltage or the ground voltage in response to an input signal in the active state while supplying an output signal of the power supply voltage in the standby state. The aforementioned semiconductor integrated circuit device further includes a plurality of second switching elements and a plurality of second precharge circuits. The plurality of second switching elements are provided in correspondence to the plurality of internal circuit groups. Each of the second switching elements is connected between the main ground line and the corresponding sub ground line, to be turned on when the corresponding internal circuit group enters the active state and turned off when the same enters the standby state. The plurality of second precharge circuits are provided in correspondence to the plurality of internal circuit groups. Each of the second precharge circuits starts precharging the corresponding sub ground line toward a second prescribed voltage lower than the power supply voltage and higher than the ground voltage before the corresponding internal circuit group enters the active state. The aforementioned semiconductor integrated circuit device, precharging the sub ground line not only on the power supply side but also on the ground side, can more quickly start operation when the internal circuit group enters the active state.
A semiconductor integrated circuit device according to a further aspect of the present invention includes a plurality of internal circuit groups, a main ground line and a plurality of sub ground lines. Each of the internal circuit groups enters an active state or a standby state. The main ground line receives a ground voltage. The plurality of sub ground lines are provided in correspondence to the plurality of internal circuit groups. Each of the internal circuit groups includes a logic circuit. The logic circuit is connected to the corresponding sub ground line for supplying an output signal of a power supply voltage or the ground voltage in response to an input signal in the active state while supplying an output signal of the power supply voltage in the standby state. The aforementioned semiconductor integrated circuit device further includes a plurality of switching elements and a plurality of precharge circuits. The plurality of switching elements are provided in correspondence to the plurality of internal circuit groups. Each of the switching elements is connected between the main ground line and the corresponding sub ground line, to be turned on when the corresponding internal circuit group enters the active state and turned off when the same enters the standby state. The plurality of precharge circuits are provided in correspondence to the plurality of internal circuit groups. Each of the precharge circuits starts precharging the corresponding sub ground line toward a prescribed voltage lower than the power supply voltage and higher than the ground voltage before the corresponding internal circuit group enters the active state.
The aforementioned semiconductor integrated circuit device, precharging the corresponding sub ground line before each internal circuit group enters the active state, can immediately start operation when the internal circuit group enters the active state.
A semiconductor integrated circuit device according to a further aspect of the present invention includes a bank decoder, a plurality of banks, a main power supply line and a plurality of sub power supply lines. The bank decoder generates a bank decode signal in response to a bank address signal. The plurality of banks are selective activated in response to the bank decode signal. The main power supply line receives a power supply voltage. The plurality of sub power supply lines are provided in correspondence to the plurality of banks. Each of the banks includes a memory cell array and a decoder. The memory cell array has a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The decoder enters an active state when the banks are activated while entering a standby state when the same are not activated, and selects the memory cells in the active state. The decoder includes a logic circuit. The logic circuit is connected to the corresponding sub power supply line for supplying an output signal of the power supply voltage or the ground voltage in response to an input signal in the active state while supplying an output signal of the ground voltage in the standby state. The aforementioned semiconductor integrated circuit device further includes a plurality of switching elements and a plurality of precharge circuits. The plurality of switching elements are provided in correspondence to the plurality of banks. Each of the switching elements is connected between the main power supply line and the corresponding sub power supply line to be turned on when the corresponding bank is activated and turned off when the same is not activated. The plurality of precharge circuits are provided in correspondence to the plurality of banks. Each of the precharge circuits starts precharging the corresponding sub power supply line toward a prescribed voltage lower than the power supply voltage and higher than the ground voltage in response to the bank decode signal when the corresponding bank is activated.
The aforementioned semiconductor integrated circuit device, precharging the sub power supply line in response to the bank decode signal, can immediately start operation when the decoder enters the active state.
Preferably, the decoder is split into a plurality of mats. Each of the sub power supply lines includes a plurality of mat sub power supply lines. The plurality of mat sub power supply lines are provided in correspondence to the plurality of mats. Each of the switching elements includes a plurality of mat switching elements. The plurality of mat switching elements are provided on correspondence to the plurality of mats. Each of the mat switching elements is connected between the main power supply line and the corresponding mat sub power supply line to be turned on when the decoder of the corresponding mat enters the active state and turned off when the same enters the standby state.
Each of the precharge circuits includes a plurality of diode elements and a plurality of switching elements. The plurality of diode elements are provided in correspondence to the plurality of mats. Each of the diode elements is forwardly connected between the main power supply line and the corresponding mat sub power supply line. The plurality of switching elements are provided in correspondence to the plurality of diode elements. Each of the switching elements is serially connected with the corresponding diode element and turned on before the decoder of the corresponding bank enters the active state.
Therefore, a voltage lower than the power supply voltage by the threshold voltage of the diode element is supplied to the mat sub power supply line, for precharging the mat sub power supply line.
Further preferably, each of the precharge circuits includes a level shift circuit and a plurality of switching elements. The level shift circuit, connected to receive the power supply voltage from the main power supply line, reduces the power supply voltage to a prescribed voltage and supplies the prescribed voltage to one of the mat sub power supply lines. The plurality of switching elements are connected between the plurality of mat sub power supply lines respectively and turned on before the corresponding bank enters the active state.
Therefore, the level shift circuit can precharge the mat sub power supply lines through the switching elements.
Further preferably, the level shift circuit includes a differential amplifier and a transistor. The differential amplifier has an input terminal connected to the main power supply line and another input terminal connected to one mat sub power supply line. The transistor is connected between the main power supply line and one mat sub power supply line, and has a gate connected to an output terminal of the differential amplifier.
Thus, the differential amplifier controls the transistor to supply a prescribed voltage to the mat sub power supply line.
Further preferably, each of the precharge circuits further includes a constant current circuit. The constant current circuit is connected between an output terminal of the level shift circuit and one mat sub power supply line.
Thus, the constant current circuit can suppress a peak current flowing from the level shift circuit to the mat sub power supply line.
Further preferably, the constant current circuit includes a resistive element, a differential amplifier and a transistor. The resistive element is connected between the output terminal of the level shift circuit and one mat sub power supply line. The differential amplifier has an input terminal connected to a terminal of the resistive element and another input terminal connected to another terminal of the resistive element. The transistor is serially connected with the resistive element, and has a gate connected to an output terminal of the differential amplifier.
Thus, the differential amplifier controls the transistor so that a current flowing through the resistive element is constant.
Further preferably, each of the precharge circuits includes a level shift circuit and a plurality of resistive elements. The level shift circuit, connected to receive the power supply voltage from the main power supply line, reduces the power supply voltage to a prescribed voltage and supplies the prescribed voltage to one of the mat sub power supply lines. The plurality of resistive elements are connected between the plurality of mat sub power supply lines respectively.
Therefore, the prescribed voltage from the level shift circuit is supplied to each mat sub power supply line through the plurality of resistive elements.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.